Typical TTL circuits incorporating a totem pole include TTL buffers, TTL output gates or devices, TTL to ECL, and ECL to TTL converters, etc. A prior art TTL output device 10 is illustrated in FIG. 1. A pullup transistor element, Darlington transistor pair Q2 and Q3, sources current from the positive TTL power supply V.sub.CC through collector resistor R4 to an output node V.sub.O. A pulldown transistor element Q4 sinks current from the output node V.sub.O to ground or low potential. The phase splitter transistor Q1 controls the conducting states of the pullup transistor element Darlington pair Q2, Q3 and the pulldown transistor element Q4 in response to high and low level logic signals at the input node V.sub.IN so that the pullup and pulldown transistor elements are generally in opposite conducting states.
The base of phase splitter transistor Q1 is coupled to the input node V.sub.IN through the diode network D1,D2,D3 which delivers base drive current to phase splitter transistor Q1 from the TTL power supply V.sub.CC through resistor R1 when the input signal at input node V.sub.IN is at the logic high level. When a logic low level signal appears at the input node V.sub.IN the phase splitter transistor Q1 is deprived of base drive current. The TTL output gate 10 of FIG. 1 is therefore inverting as a logic high level potential signal at input node V.sub.IN produces a logic low level potential signal at output node V.sub.O and vice versa.
With a high level potential signal at V.sub.IN, phase splitter Q1 conducts current from TTL power supply V.sub.CC through resistor R2. Current is diverted from the base of the Darlington transistor Q2. Phase splitter transistor Q1 drives the base of the pulldown transistor element Q4. Diode D4 helps discharge the base of Darlington transistor Q3 during the transition from high to low at the output. With a low level potential signal at V.sub.IN phase splitter transistor Q1 is not conducting, the pulldown transistor element Q4 is deprived of base drive, and current from TTL power supply V.sub.CC through resistor R2 drives the base of the pullup transistor element Q2. Resistor R3 is the discharge path for the pulldown transistor Q4.
The combination of the pullup transistor element Q2,Q3 and the pulldown transistor element Q4, generally in opposite conducting states for controlling the signal potential level at an output node V.sub.O, is known as a totem pole. A disadvantage of the totem pole presently incorporated in TTL circuits is that a temporary simultaneous conduction of the totem pole pullup and pulldown transistor elements occurs during transition from low to high level potential at the output V.sub.O. When the input signal V.sub.IN switches from high to low level potential as illustrated in FIG. 2A, pulldown transistor Q4 starts to turn off. However the Darlington pullup transistor element Q2,Q3 starts conducting while pulldown transistor Q4 is still conducting in the active region. The simultaneous conduction in the totem pole temporarily creates a low impedance path to ground from the power supply before transistor Q4 turns off and before the output signal V.sub.O rises from low to high level potential as illustrated in FIG. 2B. The result is an undesired sudden increase in the supply current or sourcing current I.sub.S from TTL power supply V.sub.CC as illustrated in FIG. 2C.
The supply current spiking in conventional TTL circuit totem pole configurations increases power dissipation and heat at the output and causes electromagnetic interference particularly when multiple TTL output devices are switching simultaneously. Another disadvantage of the conventional TTL totem pole circuit configuration, in the case of TTL output gates of the noninverting type, is that the rising ground potential or "ground bounce" caused by supply current spikes for multiple outputs reduces the noise margin for the input signal. Uncontrolled switching of the output circuit may result.